1. Technical Field
This invention relates generally to integrated circuits, and, more particularly, to a circuit for an integrated circuit memory to provide a power-on-reset function, as well as to provide the function of determining whether a plurality of page select signals for selecting a page of memory define a valid state.
2. Discussion of the Related Art
It is known to segregate the storage portion of integrated circuit memories into two or more so-called pages. For such memories, page select signals may be generated for storage and retrieval operations to the various memory pages. It is important to ensure that only one memory page is enabled during power-up, and during normal operations. In addition, access to such a memory may be made synchronously in a so-called burst mode. Commonly, such a memory may be a static random access memory (SRAM).
One approach for memory page access to implement the burst mode is to use a burst counter in combination with a postdecoder circuit to generate the above-mentioned page select signals. The generated page select signals are then applied to the memory array to access the selected page. However, such an approach may not perform fast enough under certain circumstances to meet state-of-the-art performance standards. Another approach taken in the art has been to use a combination of a decoder circuit, and a synchronous shift register. However, such a configuration may generate an invalid output under certain circumstances, for example during power-up. It is known, then, to use a global (i.e., one used for the entire integrated circuit) power-on-reset (POR) circuit to ensure that the shift register outputs a valid state (i.e., only one memory page selected at a time). However, there is no guarantee that a global power-on-reset circuit will always produce a reset pulse at power-up. This may result in the shift register powering up in an invalid state--an undesirable situation. Moreover, a global power-on-reset circuit is generally designed to generate a reset pulse on power-up only. Should the shift register somehow output an invalid state after power-up, it will not be reset to a valid state by the global power-on-reset circuit.
Accordingly, there is a need to provide an improved memory page select mechanism for use in an integrated circuit that minimizes or eliminates one or more of the problems as set forth above.